-------------------------------------------------------------------------------
-- 
--   (C) Copyright Cadence Design Systems, Inc.
-- 
--   BSDL generated by Genus(TM) Synthesis Solution 18.11-s009_1
--   Created on: Fri Aug 09 15:18:45 2019 
-- 
--   This BSDL is suitable for Cadence Test 1149.1 BSV (it includes the necessary PORT_ALIAS statement for vectored port names).
-- 
-------------------------------------------------------------------------------

entity palau_top_no_fill is
-- Entity declaration

generic (PHYSICAL_PIN_MAP : string := "UNASSIGNED");

port (
     I_TEST_EN : in bit;
     I_SPI_CLK : in bit;
     I_RESETB : linkage bit;
     IO_GPIO_7 : in bit;
     IO_GPIO_6 : in bit;
     IO_GPIO_5 : in bit;
     IO_GPIO_4 : out bit;
     IO_GPIO_3 : in bit;
     IO_GPIO_2 : in bit;
     IO_GPIO_1 : in bit;
     IO_GPIO_0 : in bit;
     IO_GPIO_8 : inout bit;
     IO_GPIO_9 : inout bit;
     IO_GPIO_10 : inout bit;
     IO_GPIO_11 : inout bit;
     IO_GPIO_12 : inout bit;
     IO_GPIO_13 : inout bit;
     IO_GPIO_14 : inout bit;
     IO_GPIO_15 : inout bit;
     IO_GPIO_16 : inout bit;
     IO_GPIO_17 : inout bit;
     IO_GPIO_18 : inout bit;
     IO_GPIO_19 : inout bit;
     IO_GPIO_20 : inout bit;
     IO_GPIO_21 : inout bit;
     IO_GPIO_22 : inout bit;
     IO_GPIO_23 : inout bit;
     IO_GPIO_ANA_0 : inout bit;
     IO_GPIO_ANA_1 : inout bit;
     IO_GPIO_ANA_2 : inout bit;
     IO_GPIO_ANA_3 : inout bit;
     IO_GPIO_ANA_4 : inout bit;
     IO_GPIO_ANA_5 : inout bit;
     IO_GPIO_ANA_6 : inout bit;
     IO_GPIO_ANA_7 : inout bit;
     IO_GPIO_ANA_8 : inout bit;
     IO_GPIO_ANA_9 : inout bit;
     IO_GPIO_ANA_10 : inout bit;
     IO_GPIO_ANA_11 : inout bit;
     IO_GPIO_ANA_12 : inout bit;
     IO_GPIO_ANA_13 : inout bit;
     IO_GPIO_ANA_14 : inout bit;
     IO_GPIO_ANA_15 : inout bit;
     O_SYNC_OUT0_N : linkage bit;
     O_SYNC_OUT0_P : out bit;
     O_SYNC_OUT1_N : linkage bit;
     O_SYNC_OUT1_P : out bit;
     I_SYNC_IN0_N : linkage bit;
     I_SYNC_IN0_P : in bit;
     I_SYNC_IN1_N : linkage bit;
     I_SYNC_IN1_P : in bit;
     I_SYNC_IN2_N : linkage bit;
     I_SYNC_IN2_P : in bit;
     I_TRX0_EN : in bit;
     I_TRX1_EN : in bit;
     I_TRX2_EN : in bit;
     I_TRX3_EN : in bit;
     I_TRX4_EN : in bit;
     I_TRX5_EN : in bit;
     I_TRX6_EN : in bit;
     I_TRX7_EN : in bit;
     I_ORX0_EN : in bit;
     I_ORX1_EN : in bit;
     O_GPINT0 : buffer bit;
     O_GPINT1 : buffer bit;
     IO_SPI_DIO : inout bit;
     I_SPI_ENB : in bit;
     O_SPI_DO : out bit;
     O_TXSER0N : buffer bit;
     O_TXSER0P : buffer bit;
     O_TXSER1N : buffer bit;
     O_TXSER1P : buffer bit;
     O_TXSER2N : buffer bit;
     O_TXSER2P : buffer bit;
     O_TXSER3N : buffer bit;
     O_TXSER3P : buffer bit;
     O_TXSER4N : buffer bit;
     O_TXSER4P : buffer bit;
     O_TXSER5N : buffer bit;
     O_TXSER5P : buffer bit;
     O_TXSER6N : buffer bit;
     O_TXSER6P : buffer bit;
     O_TXSER7N : buffer bit;
     O_TXSER7P : buffer bit;
     I_RXSER0N : in bit;
     I_RXSER0P : in bit;
     I_RXSER1N : in bit;
     I_RXSER1P : in bit;
     I_RXSER2N : in bit;
     I_RXSER2P : in bit;
     I_RXSER3N : in bit;
     I_RXSER3P : in bit;
     I_RXSER4N : in bit;
     I_RXSER4P : in bit;
     I_RXSER5N : in bit;
     I_RXSER5P : in bit;
     I_RXSER6N : in bit;
     I_RXSER6P : in bit;
     I_RXSER7N : in bit;
     I_RXSER7P : in bit
     ); 

use STD_1149_1_2001.all ;
use STD_1149_6_2003.all; -- BSDL Extension for AIO
use CDNDFT_1149_1_2001.all ;
use CDNDFT_1149_6_2003.all; -- BSDL Extension for AIO

attribute COMPONENT_CONFORMANCE of palau_top_no_fill: entity is "STD_1149_1_2001";

constant dummy : PIN_MAP_STRING :=
                                "I_TEST_EN:R14, " &
                                "I_SPI_CLK T10, " &
                                "I_RESETB:R9, " &
                                "IO_GPIO_0:H10, " &
                                "IO_GPIO_1:H11, " &
                                "IO_GPIO_2:H12, " &
                                "IO_GPIO_3:H13, " &
                                "IO_GPIO_4:J10, " &
                                "IO_GPIO_5:J11, " &
                                "IO_GPIO_6:J12, " &
                                "IO_GPIO_7:J13, " &
                                "IO_GPIO_8:K10, " &
                                "IO_GPIO_9:K13, " &
                                "IO_GPIO_10:L10, " &
                                "IO_GPIO_11:L13, " &
                                "IO_GPIO_12:M10, " &
                                "IO_GPIO_13:M13, " &
                                "IO_GPIO_14:N9, " &
                                "IO_GPIO_15:N10, " &
                                "IO_GPIO_16:N13, " &
                                "IO_GPIO_17:N14, " &
                                "IO_GPIO_18:P9, " &
                                "IO_GPIO_19:P10, " &
                                "IO_GPIO_20:P13, " &
                                "IO_GPIO_21:P14, " &
                                "IO_GPIO_22:R10, " &
                                "IO_GPIO_23:R13, " &
                                "IO_GPIO_ANA_1:D6, " &
                                "IO_GPIO_ANA_0:D7, " &
                                "IO_GPIO_ANA_2:D8, " &
                                "IO_GPIO_ANA_10:D15, " &
                                "IO_GPIO_ANA_8:D16, " &
                                "IO_GPIO_ANA_9:D17, " &
                                "IO_GPIO_ANA_6:E6, " &
                                "IO_GPIO_ANA_4:E7, " &
                                "IO_GPIO_ANA_12:E16, " &
                                "IO_GPIO_ANA_14:E17, " &
                                "IO_GPIO_ANA_5:F6, " &
                                "IO_GPIO_ANA_3:F7, " &
                                "IO_GPIO_ANA_7:F8, " &
                                "IO_GPIO_ANA_15:F15, " &
                                "IO_GPIO_ANA_11:F16, " &
                                "IO_GPIO_ANA_13:F17, " &
                                "O_SYNC_OUT0_N:U10, " &
                                "O_SYNC_OUT0_P:U9, " &
                                "O_SYNC_OUT1_N:U8, " &
                                "O_SYNC_OUT1_P:T8, " &
                                "I_SYNC_IN0_N:U13, " &
     				"I_SYNC_IN0_P:U14, " &
     				"I_SYNC_IN1_N:U15, " &
     				"I_SYNC_IN1_P:T15, " &
     				"I_SYNC_IN2_N:V10, " &
     				"I_SYNC_IN2_P:V13, " &
     				"I_TRX0_EN:H9, " &
     				"I_TRX1_EN:J9, " &
     				"I_TRX2_EN:L9, " &
     				"I_TRX3_EN:M9, " &
     				"I_TRX4_EN:H14, " &
     				"I_TRX5_EN:J14, " &
     				"I_TRX6_EN:L14, " &
     				"I_TRX7_EN:M14, " &
     				"I_ORX0_EN:K9, " &
     				"I_ORX1_EN:K14, " &
				"O_GPINT0:T9, " &
                                "O_GPINT1:T14, " &
                                "IO_SPI_DIO:T11, " &
                                "I_SPI_ENB:T13, " &
                                "O_SPI_DO:T12, " &
                                "O_TXSER0P:AA3, " &
                                "O_TXSER0N:AA4, " &
                                "O_TXSER1P:Y5, " &
                                "O_TXSER1N:Y6, " &
                                "O_TXSER2P:AC3, " &
                                "O_TXSER2N:AC4, " &
                                "O_TXSER3P:AB5, " &
                                "O_TXSER3N:AB6, " &
                                "O_TXSER4P:Y9, " &
                                "O_TXSER4N:Y10, " &
     				"O_TXSER5P:AA7, " &
     				"O_TXSER5N:AA8, " &
     				"O_TXSER6P:AB9, " &
     				"O_TXSER6N:AB10, " &
     				"O_TXSER7P:AC7, " &
     				"O_TXSER7N:AC8, " &
     				"I_RXSER0P:AA19, " &
				"I_RXSER0N:AA20, " &
     				"I_RXSER1P:Y17, " &
				"I_RXSER1N:Y18, " &
                                "I_RXSER2P:AC19, " &
                                "I_RXSER2N:AC20, " & 
                                "I_RXSER3P:AB17, " & 
                                "I_RXSER3N:AB18, " & 
                                "I_RXSER4P:AA16, " & 
                                "I_RXSER4N:AA15, " & 
                                "I_RXSER5P:Y14, " & 
                                "I_RXSER5N:Y13, " & 
                                "I_RXSER6P:AB14, " & 
                                "I_RXSER6N:AB13, " & 
                                "I_RXSER7P:AC16, " &
                                "I_RXSER7N:AC15"; 

attribute PORT_GROUPING of palau_top_no_fill: entity is 
 "Differential_Voltage ((I_RXSER0P, I_RXSER0N)," &
                       "(I_RXSER1P, I_RXSER1N)," &
                       "(I_RXSER2P, I_RXSER2N)," &
                       "(I_RXSER3P, I_RXSER3N)," &
                       "(I_RXSER4P, I_RXSER4N)," &
                       "(I_RXSER5P, I_RXSER5N)," &
                       "(I_RXSER6P, I_RXSER6N)," &
                       "(I_RXSER7P, I_RXSER7N)," &
                       "(O_TXSER0P, O_TXSER0N)," &
                       "(O_TXSER1P, O_TXSER1N)," &
                       "(O_TXSER2P, O_TXSER2N)," &
                       "(O_TXSER3P, O_TXSER3N)," &
                       "(O_TXSER4P, O_TXSER4N)," &
                       "(O_TXSER5P, O_TXSER5N)," &
                       "(O_TXSER6P, O_TXSER6N)," &
                       "(O_TXSER7P, O_TXSER7N))";

--Scan Port Identification
attribute TAP_SCAN_IN of IO_GPIO_5: signal is true;
attribute TAP_SCAN_MODE of IO_GPIO_6: signal is true;
attribute TAP_SCAN_OUT of IO_GPIO_4: signal is true;
attribute TAP_SCAN_CLOCK of IO_GPIO_7: signal is (20.0e6, BOTH);
attribute TAP_SCAN_RESET of IO_GPIO_3: signal is true;

attribute COMPLIANCE_PATTERNS of palau_top_no_fill: entity is
"(I_TEST_EN,IO_GPIO_2,IO_GPIO_1,IO_GPIO_0) (1001)";

attribute INSTRUCTION_LENGTH of palau_top_no_fill: entity is 4;

attribute INSTRUCTION_OPCODE of palau_top_no_fill: entity is
     "BYPASS         (1111)," &
     "EXTEST         (0010)," &
     "SAMPLE         (1110)," &
     "PRELOAD        (1110)," &
     "EXTEST_PULSE   (0100)," &
     "EXTEST_TRAIN   (0101)," &
     "IDCODE         (0011)," &
     "SCAN_TDR       (0110)," &
     "SCAN_WIR       (0001)," &
     "SERIAL_SCAN    (0000)," &
     "PROGRAM_WIR    (1000)" ;

attribute INSTRUCTION_CAPTURE of palau_top_no_fill: entity is "XX01";   -- req'd by Std.

attribute IDCODE_REGISTER of palau_top_no_fill: entity is
"10010010100000101010000011001011";

attribute REGISTER_ACCESS of palau_top_no_fill : entity is
"SERIAL_SCAN[1] (SERIAL_SCAN)," &
"BOUNDARY (EXTEST_PULSE,EXTEST_TRAIN)," &
"PROGRAM_WIR[1] (PROGRAM_WIR)," &
"SCAN_WIR[1] (SCAN_WIR)," &
"u_jtag_tdr_decode[8] (SCAN_TDR)" ;
attribute BOUNDARY_LENGTH of palau_top_no_fill: entity is 131; 

attribute BOUNDARY_REGISTER of palau_top_no_fill: entity is
"0  (BC_CLKIN, I_SPI_CLK, CLOCK, X)," &
"1  (BC_CLKIN, *, INTERNAL, X)," &
"2  (BC_BIDIR, IO_GPIO_8, BIDIR, X, 3, 1, Z)," &
"3  (BC_ENAB_NT, *, CONTROL, 1)," &
"4  (BC_BIDIR, IO_GPIO_9, BIDIR, X, 5, 1, Z)," &
"5  (BC_ENAB_NT, *, CONTROL, 1)," &
"6  (BC_BIDIR, IO_GPIO_10, BIDIR, X, 7, 1, Z)," &
"7  (BC_ENAB_NT, *, CONTROL, 1)," &
"8  (BC_BIDIR, IO_GPIO_11, BIDIR, X, 9, 1, Z)," &
"9  (BC_ENAB_NT, *, CONTROL, 1)," &
"10  (BC_BIDIR, IO_GPIO_12, BIDIR, X, 11, 1, Z)," &
"11  (BC_ENAB_NT, *, CONTROL, 1)," &
"12  (BC_BIDIR, IO_GPIO_13, BIDIR, X, 13, 1, Z)," &
"13  (BC_ENAB_NT, *, CONTROL, 1)," &
"14  (BC_BIDIR, IO_GPIO_14, BIDIR, X, 15, 1, Z)," &
"15  (BC_ENAB_NT, *, CONTROL, 1)," &
"16  (BC_BIDIR, IO_GPIO_15, BIDIR, X, 17, 1, Z)," &
"17  (BC_ENAB_NT, *, CONTROL, 1)," &
"18  (BC_BIDIR, IO_GPIO_16, BIDIR, X, 19, 1, Z)," &
"19  (BC_ENAB_NT, *, CONTROL, 1)," &
"20  (BC_BIDIR, IO_GPIO_17, BIDIR, X, 21, 1, Z)," &
"21  (BC_ENAB_NT, *, CONTROL, 1)," &
"22  (BC_BIDIR, IO_GPIO_18, BIDIR, X, 23, 1, Z)," &
"23  (BC_ENAB_NT, *, CONTROL, 1)," &
"24  (BC_BIDIR, IO_GPIO_19, BIDIR, X, 25, 1, Z)," &
"25  (BC_ENAB_NT, *, CONTROL, 1)," &
"26  (BC_BIDIR, IO_GPIO_20, BIDIR, X, 27, 1, Z)," &
"27  (BC_ENAB_NT, *, CONTROL, 1)," &
"28  (BC_BIDIR, IO_GPIO_21, BIDIR, X, 29, 1, Z)," &
"29  (BC_ENAB_NT, *, CONTROL, 1)," &
"30  (BC_BIDIR, IO_GPIO_22, BIDIR, X, 31, 1, Z)," &
"31  (BC_ENAB_NT, *, CONTROL, 1)," &
"32  (BC_BIDIR, IO_GPIO_23, BIDIR, X, 33, 1, Z)," &
"33  (BC_ENAB_NT, *, CONTROL, 1)," &
"34  (BC_BIDIR, IO_GPIO_ANA_0, BIDIR, X, 35, 1, Z)," &
"35  (BC_ENAB_NT, *, CONTROL, 1)," &
"36  (BC_BIDIR, IO_GPIO_ANA_1, BIDIR, X, 37, 1, Z)," &
"37  (BC_ENAB_NT, *, CONTROL, 1)," &
"38  (BC_BIDIR, IO_GPIO_ANA_2, BIDIR, X, 39, 1, Z)," &
"39  (BC_ENAB_NT, *, CONTROL, 1)," &
"40  (BC_BIDIR, IO_GPIO_ANA_3, BIDIR, X, 41, 1, Z)," &
"41  (BC_ENAB_NT, *, CONTROL, 1)," &
"42  (BC_BIDIR, IO_GPIO_ANA_4, BIDIR, X, 43, 1, Z)," &
"43  (BC_ENAB_NT, *, CONTROL, 1)," &
"44  (BC_BIDIR, IO_GPIO_ANA_5, BIDIR, X, 45, 1, Z)," &
"45  (BC_ENAB_NT, *, CONTROL, 1)," &
"46  (BC_BIDIR, IO_GPIO_ANA_6, BIDIR, X, 47, 1, Z)," &
"47  (BC_ENAB_NT, *, CONTROL, 1)," &
"48  (BC_BIDIR, IO_GPIO_ANA_7, BIDIR, X, 49, 1, Z)," &
"49  (BC_ENAB_NT, *, CONTROL, 1)," &
"50  (BC_BIDIR, IO_GPIO_ANA_8, BIDIR, X, 51, 1, Z)," &
"51  (BC_ENAB_NT, *, CONTROL, 1)," &
"52  (BC_BIDIR, IO_GPIO_ANA_9, BIDIR, X, 53, 1, Z)," &
"53  (BC_ENAB_NT, *, CONTROL, 1)," &
"54  (BC_BIDIR, IO_GPIO_ANA_10, BIDIR, X, 55, 1, Z)," &
"55  (BC_ENAB_NT, *, CONTROL, 1)," &
"56  (BC_BIDIR, IO_GPIO_ANA_11, BIDIR, X, 57, 1, Z)," &
"57  (BC_ENAB_NT, *, CONTROL, 1)," &
"58  (BC_BIDIR, IO_GPIO_ANA_12, BIDIR, X, 59, 1, Z)," &
"59  (BC_ENAB_NT, *, CONTROL, 1)," &
"60  (BC_BIDIR, IO_GPIO_ANA_13, BIDIR, X, 61, 1, Z)," &
"61  (BC_ENAB_NT, *, CONTROL, 1)," &
"62  (BC_BIDIR, IO_GPIO_ANA_14, BIDIR, X, 63, 1, Z)," &
"63  (BC_ENAB_NT, *, CONTROL, 1)," &
"64  (BC_BIDIR, IO_GPIO_ANA_15, BIDIR, X, 65, 1, Z)," &
"65  (BC_ENAB_NT, *, CONTROL, 1)," &
"66  (BC_OUT, O_SYNC_OUT0_P, OUTPUT2, X)," &
"67  (BC_11496_OUT, *, INTERNAL, X)," &
"68  (BC_OUT, O_SYNC_OUT1_P, OUTPUT2, X)," &
"69  (BC_11496_OUT, *, INTERNAL, X)," &
"70  (BC_IN, I_SYNC_IN0_P, INPUT, X)," &
"71  (BC_IN, *, INTERNAL, X)," &
"72  (BC_11496_ACTR, *, INTERNAL, X)," &
"73  (BC_11496_ACTR, *, INTERNAL, X)," &
"74  (BC_IN, I_SYNC_IN1_P, INPUT, X)," &
"75  (BC_IN, *, INTERNAL, X)," &
"76  (BC_11496_ACTR, *, INTERNAL, X)," &
"77  (BC_11496_ACTR, *, INTERNAL, X)," &
"78  (BC_IN, I_SYNC_IN2_P, INPUT, X)," &
"79  (BC_IN, *, INTERNAL, X)," &
"80  (BC_11496_ACTR, *, INTERNAL, X)," &
"81  (BC_11496_ACTR, *, INTERNAL, X)," &
"82  (BC_IN, I_TRX0_EN, INPUT, X)," &
"83  (BC_IN, I_TRX1_EN, INPUT, X)," &
"84  (BC_IN, I_TRX2_EN, INPUT, X)," &
"85  (BC_IN, I_TRX3_EN, INPUT, X)," &
"86  (BC_IN, I_TRX4_EN, INPUT, X)," &
"87  (BC_IN, I_TRX5_EN, INPUT, X)," &
"88  (BC_IN, I_TRX6_EN, INPUT, X)," &
"89  (BC_IN, I_TRX7_EN, INPUT, X)," &
"90  (BC_IN, I_ORX0_EN, INPUT, X)," &
"91  (BC_IN, I_ORX1_EN, INPUT, X)," &
"92  (BC_OUT, O_GPINT0, OUTPUT2, X)," &
"93  (BC_OUT, O_GPINT1, OUTPUT2, X)," &
"94  (BC_BIDIR, IO_SPI_DIO, BIDIR, X, 95, 1, Z)," &
"95  (BC_ENAB_NT, *, CONTROL, 1)," &
"96  (BC_IN, I_SPI_ENB, INPUT, X)," &
"97  (BC_OUT, O_SPI_DO, OUTPUT3, X, 98, 1, Z)," &
"98  (BC_ENAB_NT, *, CONTROL, 1)," &
"99  (BC_11496_OUT, O_TXSER0P, OUTPUT2, X)," &
"100  (BC_11496_OUT, O_TXSER1P, OUTPUT2, X)," &
"101  (BC_11496_OUT, O_TXSER2P, OUTPUT2, X)," &
"102  (BC_11496_OUT, O_TXSER3P, OUTPUT2, X)," &
"103  (BC_11496_OUT, O_TXSER4P, OUTPUT2, X)," &
"104  (BC_11496_OUT, O_TXSER5P, OUTPUT2, X)," &
"105  (BC_11496_OUT, O_TXSER6P, OUTPUT2, X)," &
"106  (BC_11496_OUT, O_TXSER7P, OUTPUT2, X)," &
"107  (BC_IN, *, INTERNAL, X)," &
"108  (BC_11496_ACTR, I_RXSER0P, OBSERVE_ONLY, X)," &
"109  (BC_11496_ACTR, I_RXSER0N, OBSERVE_ONLY, X)," &
"110  (BC_IN, *, INTERNAL, X)," &
"111  (BC_11496_ACTR, I_RXSER1P, OBSERVE_ONLY, X)," &
"112  (BC_11496_ACTR, I_RXSER1N, OBSERVE_ONLY, X)," &
"113  (BC_IN, *, INTERNAL, X)," &
"114  (BC_11496_ACTR, I_RXSER2P, OBSERVE_ONLY, X)," &
"115  (BC_11496_ACTR, I_RXSER2N, OBSERVE_ONLY, X)," &
"116  (BC_IN, *, INTERNAL, X)," &
"117  (BC_11496_ACTR, I_RXSER3P, OBSERVE_ONLY, X)," &
"118  (BC_11496_ACTR, I_RXSER3N, OBSERVE_ONLY, X)," &
"119  (BC_IN, *, INTERNAL, X)," &
"120  (BC_11496_ACTR, I_RXSER4P, OBSERVE_ONLY, X)," &
"121  (BC_11496_ACTR, I_RXSER4N, OBSERVE_ONLY, X)," &
"122  (BC_IN, *, INTERNAL, X)," &
"123  (BC_11496_ACTR, I_RXSER5P, OBSERVE_ONLY, X)," &
"124  (BC_11496_ACTR, I_RXSER5N, OBSERVE_ONLY, X)," &
"125  (BC_IN, *, INTERNAL, X)," &
"126  (BC_11496_ACTR, I_RXSER6P, OBSERVE_ONLY, X)," &
"127  (BC_11496_ACTR, I_RXSER6N, OBSERVE_ONLY, X)," &
"128  (BC_IN, *, INTERNAL, X)," &
"129  (BC_11496_ACTR, I_RXSER7P, OBSERVE_ONLY, X)," &
"130  (BC_11496_ACTR, I_RXSER7N, OBSERVE_ONLY, X)";

attribute BOUNDARY_SCAN_DESIGN_TYPE: BSDL_EXTENSION;

attribute BOUNDARY_SCAN_DESIGN_TYPE of palau_top_no_fill: entity is "IEEE_11496";

attribute AIO_COMPONENT_CONFORMANCE of palau_top_no_fill: entity is "STD_1149_6_2003";

attribute AIO_PIN_BEHAVIOR of palau_top_no_fill : entity is
     "O_TXSER0P, O_TXSER1P, O_TXSER2P;" &
     "O_TXSER3P, O_TXSER4P, O_TXSER5P, O_TXSER6P;" &
     "I_RXSER0P[108] : LP_time=5.0e-9, I_RXSER1P[111] : LP_time=5.0e-9, I_RXSER2P[114] : LP_time=5.0e-9, I_RXSER3P[117] : LP_time=5.0e-9;" &
     "I_RXSER4P[120] : LP_time=5.0e-9, I_RXSER5P[123] : LP_time=5.0e-9, I_RXSER6P[126] : LP_time=5.0e-9, I_RXSER7P[129] : LP_time=5.0e-9;" &
     "O_TXSER7P " ;

attribute TestBench_Port_Alias: BSDL_EXTENSION;

attribute TestBench_Port_Alias of palau_top_no_fill: entity is
"u_bscan__gpio_oen_to_EDI_1:\u_bscan__gpio_oen_to_EDI[1]," &
"u_bscan__gpio_oen_to_EDI_2:\u_bscan__gpio_oen_to_EDI[2]," &
"u_bscan__gpio_oen_to_EDI_3:\u_bscan__gpio_oen_to_EDI[3]," &
"u_bscan__gpio_oen_to_EDI_4:\u_bscan__gpio_oen_to_EDI[4]," &
"u_bscan__gpio_oen_to_EDI_5:\u_bscan__gpio_oen_to_EDI[5]," &
"u_bscan__gpio_oen_to_EDI_6:\u_bscan__gpio_oen_to_EDI[6]," &
"u_bscan__gpio_oen_to_EDI_7:\u_bscan__gpio_oen_to_EDI[7]," &
"u_bscan__gpio_oen_to_EDI_8:\u_bscan__gpio_oen_to_EDI[8]," &
"u_bscan__gpio_oen_to_EDI_9:\u_bscan__gpio_oen_to_EDI[9]," &
"u_bscan__gpio_oen_to_EDI_10:\u_bscan__gpio_oen_to_EDI[10]," &
"u_bscan__gpio_oen_to_EDI_11:\u_bscan__gpio_oen_to_EDI[11]," &
"u_bscan__gpio_oen_to_EDI_12:\u_bscan__gpio_oen_to_EDI[12]," &
"u_bscan__gpio_oen_to_EDI_13:\u_bscan__gpio_oen_to_EDI[13]," &
"u_bscan__gpio_oen_to_EDI_14:\u_bscan__gpio_oen_to_EDI[14]," &
"u_bscan__gpio_oen_to_EDI_15:\u_bscan__gpio_oen_to_EDI[15]," &
"u_bscan__gpio_oen_to_EDI_16:\u_bscan__gpio_oen_to_EDI[16]," &
"u_bscan__ana_oen_to_EDI_0:\u_bscan__ana_oen_to_EDI[0]," &
"u_bscan__ana_oen_to_EDI_1:\u_bscan__ana_oen_to_EDI[1]," &
"u_bscan__ana_oen_to_EDI_2:\u_bscan__ana_oen_to_EDI[2]," &
"u_bscan__ana_oen_to_EDI_3:\u_bscan__ana_oen_to_EDI[3]," &
"u_bscan__ana_oen_to_EDI_4:\u_bscan__ana_oen_to_EDI[4]," &
"u_bscan__ana_oen_to_EDI_5:\u_bscan__ana_oen_to_EDI[5]," &
"u_bscan__ana_oen_to_EDI_6:\u_bscan__ana_oen_to_EDI[6]," &
"u_bscan__ana_oen_to_EDI_7:\u_bscan__ana_oen_to_EDI[7]," &
"u_bscan__ana_oen_to_EDI_8:\u_bscan__ana_oen_to_EDI[8]," &
"u_bscan__ana_oen_to_EDI_9:\u_bscan__ana_oen_to_EDI[9]," &
"u_bscan__ana_oen_to_EDI_10:\u_bscan__ana_oen_to_EDI[10]," &
"u_bscan__ana_oen_to_EDI_11:\u_bscan__ana_oen_to_EDI[11]," &
"u_bscan__ana_oen_to_EDI_12:\u_bscan__ana_oen_to_EDI[12]," &
"u_bscan__ana_oen_to_EDI_13:\u_bscan__ana_oen_to_EDI[13]," &
"u_bscan__ana_oen_to_EDI_14:\u_bscan__ana_oen_to_EDI[14]," &
"u_bscan__ana_oen_to_EDI_15:\u_bscan__ana_oen_to_EDI[15]," &
"u_bscan__oen_to_EDI_0:\u_bscan__oen_to_EDI[0]," &
"u_bscan__oen_to_EDI_1:\u_bscan__oen_to_EDI[1]," &
"u_bscan__gpio_oen_to_EDI_0:\u_bscan__gpio_oen_to_EDI[0]," &
"u_bscan__oen_to_EDI_2:\u_bscan__oen_to_EDI[2]";

end palau_top_no_fill ;
